1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing an SOI (Silicon-On-Insulator) substrate and a method of manufacturing the same.
2. Description of the Background Art
Attention has been given to a semiconductor device (SOI device) employing an SOI substrate as a high-operating-speed, low-power-consumption device. The SOI substrate has a multi-layer structure including a semiconductor substrate, an insulation layer and a semiconductor layer which are stacked in the order named. An SOI device (thin-film SOI device) having a semiconductor layer thinned to about several micrometers has recently received particular attention, and has been expected to be applied to LSI circuits for portable equipment.
FIG. 44 is a sectional view showing a structure of a background art semiconductor device. An SOI substrate 104 has a multi-layer structure such that a silicon substrate 101, a BOX (Buried OXide) layer 102 and a silicon layer 103 are stacked in the order named. An isolating insulation film 105 made of silicon oxide is partially formed in the silicon layer 103. The isolating insulation film 105 extends from the upper surface of the silicon layer 103 to the upper surface of the BOX layer 102. The isolating insulation film having such a configuration is referred to as a “completely isolating insulation film.”
A MOSFET is formed in a device region defined by the isolating insulation film 105 in a manner to be specifically described below. A silicon oxide film 106 is formed partially on the upper surface of the silicon layer 103. A gate electrode 107 made of polysilicon is formed partially on the silicon oxide film 106. A portion of the silicon oxide film 106 which lies under the gate electrode 107 functions as a gate insulation film. A silicon nitride film 109 is formed on each side surface of the gate electrode 107, with a silicon oxide film 108 therebetween. The silicon oxide films 108 are formed not only between the side surfaces of the gate electrode 107 and side surfaces of the silicon nitride films 109 but also between the upper surface of the silicon oxide film 106 and the lower surface of the silicon nitride films 109.
A pair of source/drain regions 110 are formed in the silicon layer 103. A region between the pair of source/drain regions 110 is defined as a body region 112. Each of the source/drain regions 110 has an extension 111 extending to under the gate electrode 107 in the upper surface of the silicon layer 103.
FIG. 45 is a sectional view showing a structure of another background art semiconductor device. The semiconductor device shown in FIG. 45 has an isolating insulation film 130 made of silicon oxide in place of the completely isolating insulation film 105 shown in FIG. 44. The lower surface of the isolating insulation film 130 does not reach the upper surface of the BOX layer 102. The isolating insulation film having such a configuration is referred to as a “partially isolating insulation film.” The remaining structure of the semiconductor device shown in FIG. 45 is similar to the corresponding structure of the semiconductor device shown in FIG. 44.
FIG. 46 is a schematic top plan view showing a top surface structure of the semiconductor device shown in FIG. 45. The use of the partially isolating insulation film 130 allows the body region 112 to be tied to a fixed potential through a portion of the silicon layer 103 which lies between the lower surface of the isolating insulation film 130 and the upper surface of the BOX layer 102 from a body contact region 150. This suppresses a so-called floating body effect such as the occurrence of a kink effect and variations in delay time depending on an operating frequency.
Referring again to FIGS. 44 and 45, the width W101 of the silicon oxide film 108 in a direction of the gate length (or in the lateral direction as viewed in the drawings) is less than the total thickness T101 of the silicon oxide film 106 and the silicon oxide film 108. In some cases, however, a portion of the silicon oxide film 106 other than functioning as the gate insulation film (i.e., a portion of the silicon oxide film 106 which lies between the lower surface of the silicon oxide film 108 and the upper surface of the silicon layer 103 as viewed in FIG. 44) is removed away during a gate etching process, in which case the width W101 is equal to the total thickness T101. Thus, the width W101 is not greater than the total thickness T101 in the background art semiconductor devices.
Unfortunately, in such background art semiconductor devices, the relatively small width W101 of the silicon oxide film 108 results in a relatively short distance L101 between the pair of source/drain regions 110 (more specifically, between the pair of extensions 111).
In the semiconductor devices shown in FIGS. 44 and 45, there is a parasitic bipolar transistor with the source/drain regions 110 serving as an emitter and a collector and the body region 112 serving as a base. The short distance L101 between the pair of source/drain regions 110 means a small base width of the parasitic bipolar transistor, resulting in high gain of the parasitic bipolar transistor. As a result, the background art semiconductor devices present a problem such that there is a danger that the high gain of the parasitic bipolar transistor causes a malfunction and a variation in operating characteristics of the MOSFET.